The present invention relates to a semiconductor memory apparatus such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) as well as relates to a self-repair method adopted in the semiconductor memory apparatus. More particularly, the present invention relates to a semiconductor memory apparatus having a redundancy search circuit for replacing a bad (defective) memory cell with a redundant memory cell included in the semiconductor memory apparatus in advance as well as relates to a self-repair method adopted in the semiconductor memory apparatus.
In a semiconductor memory apparatus such as a DRAM, the integration scale is extremely large and, in consequence, the yield becomes a problem. Practically, it is almost impossible to increase the yield to 100% so that one may assume that a defective memory cell always exists in a semiconductor memory apparatus. A defective memory cell is also referred to hereafter as an abnormal bit. If a defective memory cell exists in a semiconductor memory apparatus, however, the apparatus cannot of course be shipped as a product.
In order to solve the problem described above, in actuality, some spare memory cells are provided in advance and, if a defective memory cell is detected, the defective cell is replaced with one of the spare memory cells to rescue the semiconductor memory apparatus. To put it concretely, spare memory cells are redundantly provided to form a redundant line and, if a defective memory cell exists, a bit or address line including the defective memory cell is replaced with the redundant line. In the case of the conventional semiconductor memory apparatus, a memory cell is determined to be normal or defective at a stage of shipping the memory apparatus from the factory by using a memory tester external to the semiconductor memory apparatus at the factory.
In the mean time, LSI technologies have been improved substantially in recent years. With the improvement of the LSI technologies, the number of apparatuses, in which a plurality of memories coexists with logic circuits in the same LSI chip, increases. It is thus practically difficult to test the individual memories of the same LSI chip independently of each other. In addition, as the operating speed of the LSI chip becomes higher, it becomes difficult to evaluate the performance of a memory by using an external memory tester. For these reasons, a memory-testing method embedded in an LSI chip is indispensable to the chip. In addition, even if a memory can be tested by using an external memory tester, such a memory tester is extremely expensive. Thus, since the cost of testing a memory in a fabrication process has been increasing considerably in recent years, it is desirable to provide a method, which allows an LSI a memory to be tested at a high speed equal to the operating speed of the LSI chip and can be implemented at a low cost.
With regard to the testing and evaluation of a semiconductor memory apparatus, as described earlier, each bit or each memory cell in an LSI chip is evaluated to determine whether the bit or the cell is normal or defective. A portion embedded in the LSI chip as a portion for evaluating memory cells is generally referred to as a BIST (Built-In Self Test) circuit. In the current situation, test circuits available in the market are mostly provided for SRAMs, and each manufacturer is developing a DRAM-oriented test circuit suitable for the original DRAM architecture of the manufacturer.
The BIST circuit determines whether or not an abnormal (defective or bad) bit (memory cell) exists in a memory and, if an abnormal bit exists, determines what address the bit is located at. A semiconductor memory apparatus includes a dummy bit or word line to restore the abnormal bit detected by the BIST circuit. The dummy bit or word line is referred to as a redundant line. The BIST circuit carries out processing only to find an abnormal bit. Thus, a later process determines how a redundant line is actually used.
A plurality of redundant lines is provided in the column and row directions. It is therefore necessary to determine how an abnormal bit is to be interpolated by using a redundant line and which redundant line is to be used for interpolating the abnormal bit. The work to interpolate an abnormal bit by using a redundant line as such is referred to as a repair and the work to determine which redundant line is to be used for interpolating an abnormal bit is referred to as a repair search. The work to actually complete a repair after determining a mask address in an LSI chip is referred to as a BISR (Built-In Self-Repair) or merely a self-repair.
If an external memory tester is used, a repair-search calculation is carried out by using a computer employed in the external memory tester. For more information, refer to documents such as patent reference 1. Besides the evaluation function to determine whether or not an abnormal bit exists, a repair-search (redundancy-analysis) function is added to the BIST circuit embedded in an LSI chip. The repair-search (redundancy-analysis) function is a function to determine which redundant line is to be used for interpolating an abnormal bit. For more information, refer to documents such as patent reference 2.
[Patent Document 1]
Japanese Patent Laid-open No. Hei 7-146340
[Patent Document 2]
Japanese Patent Laid-open No. 2002-117697
Even in the case of an LSI chip including an embedded BIST circuit, however, a problem remains to be solved if the chip is tested in a configuration wherein information on normality/abnormality for each bit is transferred to a memory of an external computer and the external computer is used for carrying out a repair-search calculation as is the case with the conventional technology disclosed in patent reference 1. This is because a memory with a large storage capacity for storing the information on normality/abnormality for each bit is required of the external computer and it takes very long time to carry out the calculation.
Even if the BIST circuit embedded in the LSI chip is provided with a repair-search function as is the case with the conventional technology disclosed in patent reference 2, a plurality of repairable combination types is conceivable. In an example given in the reference, the number of repairable combination types is 6. This technology adopts a technique whereby a storage location for storing addresses for all these combinations is provided and repair possibility for all the 6 types is verified at the same time. Thus, the scale of the circuit conceivably increases.